Add original unix v6
This commit is contained in:
memnoth
+300
@@ -0,0 +1,300 @@
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#
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/*
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*/
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/*
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* DH-11 driver
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* This driver calls on the DHDM driver.
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* If the DH has no DM11-BB, then the latter will
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* be fake. To insure loading of the correct DM code,
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* lib2 should have dhdm.o, dh.o and dhfdm.o in that order.
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*/
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#include "../param.h"
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#include "../conf.h"
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#include "../user.h"
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#include "../tty.h"
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#include "../proc.h"
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#define DHADDR 0160020
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#define NDH11 16 /* number of lines */
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#define DHNCH 8 /* max number of DMA chars */
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struct tty dh11[NDH11];
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/*
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* Place from which to do DMA on output
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*/
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char dh_clist[NDH11][DHNCH];
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/*
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* Used to communicate the number of lines to the DM
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*/
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int ndh11 NDH11;
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/*
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* Hardware control bits
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*/
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#define BITS6 01
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#define BITS7 02
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#define BITS8 03
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#define TWOSB 04
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#define PENABLE 020
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/* DEC manuals incorrectly say this bit causes generation of even parity. */
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#define OPAR 040
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#define HDUPLX 040000
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#define IENABLE 030100
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#define PERROR 010000
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#define FRERROR 020000
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#define XINT 0100000
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#define SSPEED 7 /* standard speed: 300 baud */
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/*
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* Software copy of last dhbar
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*/
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int dhsar;
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struct dhregs {
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int dhcsr;
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int dhnxch;
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int dhlpr;
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int dhcar;
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int dhbcr;
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int dhbar;
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int dhbreak;
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int dhsilo;
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};
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/*
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* Open a DH11 line.
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*/
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dhopen(dev, flag)
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{
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register struct tty *tp;
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extern dhstart();
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if (dev.d_minor >= NDH11) {
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u.u_error = ENXIO;
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return;
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}
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tp = &dh11[dev.d_minor];
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tp->t_addr = dhstart;
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tp->t_dev = dev;
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DHADDR->dhcsr =| IENABLE;
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tp->t_state =| WOPEN|SSTART;
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if ((tp->t_state&ISOPEN) == 0) {
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tp->t_erase = CERASE;
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tp->t_kill = CKILL;
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tp->t_speeds = SSPEED | (SSPEED<<8);
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tp->t_flags = ODDP|EVENP|ECHO;
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dhparam(tp);
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}
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dmopen(dev);
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tp->t_state =& ~WOPEN;
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tp->t_state =| ISOPEN;
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if (u.u_procp->p_ttyp == 0)
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u.u_procp->p_ttyp = tp;
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}
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/*
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* Close a DH11 line.
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*/
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dhclose(dev)
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{
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register struct tty *tp;
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tp = &dh11[dev.d_minor];
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dmclose(dev);
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tp->t_state =& (CARR_ON|SSTART);
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wflushtty(tp);
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}
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/*
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* Read from a DH11 line.
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*/
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dhread(dev)
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{
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ttread(&dh11[dev.d_minor]);
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}
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/*
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* write on a DH11 line
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*/
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dhwrite(dev)
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{
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ttwrite(&dh11[dev.d_minor]);
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}
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/*
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* DH11 receiver interrupt.
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*/
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dhrint()
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{
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register struct tty *tp;
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register int c;
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while ((c = DHADDR->dhnxch) < 0) { /* char. present */
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tp = &dh11[(c>>8)&017];
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if (tp >= &dh11[NDH11])
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continue;
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if((tp->t_state&ISOPEN)==0 || (c&PERROR)) {
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wakeup(tp);
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continue;
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}
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if (c&FRERROR) /* break */
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if (tp->t_flags&RAW)
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c = 0; /* null (for getty) */
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else
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c = 0177; /* DEL (intr) */
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ttyinput(c, tp);
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}
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}
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/*
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* stty/gtty for DH11
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*/
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dhsgtty(dev, av)
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int *av;
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{
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register struct tty *tp;
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register r;
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tp = &dh11[dev.d_minor];
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if (ttystty(tp, av))
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return;
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dhparam(tp);
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}
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/*
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* Set parameters from open or stty into the DH hardware
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* registers.
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*/
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dhparam(atp)
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struct tty *atp;
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{
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register struct tty *tp;
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register int lpr;
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tp = atp;
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spl5();
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DHADDR->dhcsr.lobyte = tp->t_dev.d_minor | IENABLE;
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/*
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* Hang up line?
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*/
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if (tp->t_speeds.lobyte==0) {
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tp->t_flags =| HUPCL;
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dmclose(tp->t_dev);
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return;
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}
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lpr = (tp->t_speeds.hibyte<<10) | (tp->t_speeds.lobyte<<6);
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if (tp->t_speeds.lobyte == 4) /* 134.5 baud */
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lpr =| BITS6|PENABLE|HDUPLX; else
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if (tp->t_flags&EVENP)
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if (tp->t_flags&ODDP)
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lpr =| BITS8; else
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lpr =| BITS7|PENABLE; else
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lpr =| BITS7|OPAR|PENABLE;
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if (tp->t_speeds.lobyte == 3) /* 110 baud */
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lpr =| TWOSB;
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DHADDR->dhlpr = lpr;
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spl0();
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}
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/*
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* DH11 transmitter interrupt.
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* Restart each line which used to be active but has
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* terminated transmission since the last interrupt.
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*/
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dhxint()
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{
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register struct tty *tp;
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register ttybit, bar;
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bar = dhsar & ~DHADDR->dhbar;
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DHADDR->dhcsr =& ~XINT;
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ttybit = 1;
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for (tp = dh11; bar; tp++) {
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if(bar&ttybit) {
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dhsar =& ~ttybit;
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bar =& ~ttybit;
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tp->t_state =& ~BUSY;
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dhstart(tp);
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}
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ttybit =<< 1;
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}
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}
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/*
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* Start (restart) transmission on the given DH11 line.
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*/
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dhstart(atp)
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struct tty *atp;
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{
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extern ttrstrt();
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register c, nch;
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register struct tty *tp;
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int sps;
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char *cp;
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sps = PS->integ;
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spl5();
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tp = atp;
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/*
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* If it's currently active, or delaying,
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* no need to do anything.
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*/
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if (tp->t_state&(TIMEOUT|BUSY))
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goto out;
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/*
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* t_char is a delay indicator which may have been
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* left over from the last start.
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* Arrange for the delay.
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*/
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if (c = tp->t_char) {
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tp->t_char = 0;
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timeout(ttrstrt, tp, (c&0177)+6);
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tp->t_state =| TIMEOUT;
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goto out;
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}
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cp = dh_clist[tp->t_dev.d_minor];
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nch = 0;
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/*
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* Copy DHNCH characters, or up to a delay indicator,
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* to the DMA area.
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*/
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while (nch > -DHNCH && (c = getc(&tp->t_outq))>=0) {
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if (c >= 0200) {
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tp->t_char = c;
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break;
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}
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*cp++ = c;
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nch--;
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}
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/*
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* If the writer was sleeping on output overflow,
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* wake him when low tide is reached.
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*/
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if (tp->t_outq.c_cc<=TTLOWAT && tp->t_state&ASLEEP) {
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tp->t_state =& ~ASLEEP;
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wakeup(&tp->t_outq);
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}
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/*
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* If any characters were set up, start transmission;
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* otherwise, check for possible delay.
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*/
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if (nch) {
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DHADDR->dhcsr.lobyte = tp->t_dev.d_minor | IENABLE;
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DHADDR->dhcar = cp+nch;
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DHADDR->dhbcr = nch;
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c = 1<<tp->t_dev.d_minor;
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DHADDR->dhbar =| c;
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dhsar =| c;
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tp->t_state =| BUSY;
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} else if (c = tp->t_char) {
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tp->t_char = 0;
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timeout(ttrstrt, tp, (c&0177)+6);
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tp->t_state =| TIMEOUT;
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}
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out:
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PS->integ = sps;
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}
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